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74lv373 octal d-type transparent latch (3-state) product specification supersedes data of 1997 march 04 ic24 data handbook 1998 jun 10 integrated circuits
philips semiconductors product specification 74lv373 octal d-type transparent latch (3-state) 2 1998 jun 10 8531934 19545 features ? wide operating voltage: 1.0 to 5.5v ? optimized for low voltage applications: 1.0v to 3.6v ? accepts ttl input levels between v cc = 2.7v and v cc = 3.6v ? typical v olp (output ground bounce) < 0.8v at v cc = 3.3v, t amb = 25 c ? typical v ohv (output v oh undershoot) > 2v at v cc = 3.3v, t amb = 25 c ? common 3-state output enable input ? output capability: bus driver ? i cc category: msi description the 74lv373 is a low-voltage si-gate cmos device that is pin and function compatible with 74hc/hct373. the 74lv373 is an octal d-type transparent latch featuring separate d-type inputs for each latch and 3-state outputs for bus oriented applications. a latch enable (le) input and an output enable (oe ) input are common to all internal latches. the `373' consists of eight d-type transparent latches with 3-state true outputs. when le is high, data at the dn inputs enters the latches. in this condition the latches are transparent, i.e., a latch output will change each time its corresponding d-input changes. when le is low the latches store the information that was present at the d-inputs a set-up time preceding the high-to-low transition of le. when oe is low, the contents of the eight latches are available at the outputs. when oe is high, the outputs go to the high impedance off-state. operation of the oe input does not affect the state of the latches. the `373' is functionally identical to the `573', but the `573' has a different pin arrangement. quick reference data gnd = 0v; t amb = 25 c; t r = t f 2.5 ns symbol parameter conditions typical unit t phl /t plh propagation delay d n to q n le to q n c l = 15pf v cc = 3.3v 10 12 ns c i input capacitance 3.5 pf c pd power dissipation capacitance per latch notes 1, 2 22 pf notes: 1. c pd is used to determine the dynamic power dissipation (p d in m w) p d = c pd v cc 2 x f i (c l v cc 2 f o ) where: f i = input frequency in mhz; c l = output load capacity in pf; f o = output frequency in mhz; v cc = supply voltage in v; (c l v cc 2 f o ) = sum of the outputs. 2. the condition is v i = gnd to v cc. ordering and package information packages temperature range outside north america north america pkg. dwg. # 20-pin plastic dil 40 c to +125 c 74lv373 n 74lv373 n sot146-1 20-pin plastic so 40 c to +125 c 74lv373 d 74lv373 d sot163-1 20-pin plastic ssop type ii 40 c to +125 c 74lv373 db 74lv373 db sot339-1 20-pin plastic tssop type i 40 c to +125 c 74lv373 pw 74lv373pw dh sot360-1 pin description pin number symbol function 1 oe output enabled input (active low) 2, 5, 6, 9, 12, 15, 16, 19 q 0 q 7 3-state latch outputs 3, 4, 7, 8, 13, 14, 17, 18 d 0 d 7 data inputs 10 gnd ground (0v) 11 le latch enable input (active high) 20 v cc positive supply voltage
philips semiconductors product specification 74lv373 octal d-type transparent latch (3-state) 1998 jun 10 3 pin configuration sv00657 q 0 q 1 q 2 q 3 gnd q 4 q 5 q 6 q 7 d 0 d 1 d 2 d 3 v cc d 4 d 5 d 6 d 7 le 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 oe logic symbol sv00658 q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 le 2 5 6 9 12 15 16 19 11 3 4 7 8 13 14 17 18 1 oe logic symbol (ieee/iec) sv00659 2 5 6 9 12 15 16 19 3 4 7 8 13 14 17 18 c1 en1 1d 11 1 functional diagram sv00660 q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 le 1 latch 1 to 8 3state outputs 2 5 6 9 12 15 16 19 3 4 7 8 13 14 17 18 11 oe logic diagram latch 1 d q le le q0 d 0 latch 2 d q le le q1 d 1 latch 3 d q le le q2 d 2 latch 4 d q le le q3 d 3 latch 5 d q le le q4 d 4 latch 6 d q le le q5 d 5 latch 7 d q le le q6 d 6 latch 8 d q le le q7 d 7 le oe sv00661
philips semiconductors product specification 74lv373 octal d-type transparent latch (3-state) 1998 jun 10 4 function table operating modes inputs internal outputs operating modes oe le dn latches q 0 to q 7 enable and read register (transparent mode) l l h h l h l h l h latch and read register l l l l i h l h l h latch register and disable outputs h h l l i h l h z z h = high voltage level h = high voltage level one set-up time prior to the high-to-low le transition l = low voltage level i = low voltage level one set-up time prior to the high-to-low le transition x = don't care z = high impedance off-state recommended operating conditions symbol parameter conditions min typ. max unit v cc dc supply voltage see note1 1.0 3.3 5.5 v v i input voltage 0 v cc v v o output voltage 0 v cc v t amb operating ambient temperature range in free air see dc and ac characteristics 40 40 +85 +125 c t r , t f input rise and fall times v cc = 1.0v to 2.0v v cc = 2.0v to 2.7v v cc = 2.7v to 3.6v v cc = 3.6v to 5.5v 500 200 100 50 ns/v note: 1. the lv is guaranteed to function down to v cc = 1.0v (input levels gnd or v cc ); dc characteristics are guaranteed from v cc = 1.2v to v cc = 5.5v. absolute maximum ratings 1, 2 in accordance with the absolute maximum rating system (iec 134). voltages are referenced to gnd (ground = 0v). symbol parameter conditions rating unit v cc dc supply voltage 0.5 to +7.0 v i ik dc input diode current v i < 0.5 or v i > v cc + 0.5v 20 ma i ok dc output diode current v o < 0.5 or v o > v cc + 0.5v 50 ma i o dc output source or sink current bus driver outputs 0.5v < v o < v cc + 0.5v 35 ma i gnd , i cc dc v cc or gnd current for types with bus driver outputs 70 ma t stg storage temperature range 65 to +150 c power dissipation per package for temperature range: 40 to +125 c p tt plastic dil above +70 c derate linearly with 12mw/k 750 mw p tot plastic mini-pack (so) above +70 c derate linearly with 8 mw/k 500 mw plastic shrink mini-pack (ssop and tssop) above +60 c derate linearly with 5.5 mw/k 400 notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposur e to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the input and output voltage ratings may be exceeded if the input and output current ratings are observed.
philips semiconductors product specification 74lv373 octal d-type transparent latch (3-state) 1998 jun 10 5 dc characteristics over recommended operating conditions. voltages are referenced to gnd (ground = 0v). limits symbol parameter test conditions -40 c to +85 c -40 c to +125 c unit min typ 1 max min max v cc = 1.2v 0.9 0.9 v high level input v cc = 2.0v 1.4 1.4 v v ih voltage v cc = 2.7 to 3.6v 2.0 2.0 v v cc = 4.5 to 5.5v 0.7*v cc 0.7*v cc v cc = 1.2v 0.3 0.3 v low level input v cc = 2.0v 0.6 0.6 v v il voltage v cc = 2.7 to 3.6v 0.8 0.8 v v cc = 4.5 to 5.5 0.3*v cc 0.3*v cc v cc = 1.2v; v i = v ih or v il; i o = 100 m a 1.2 high l l t t v cc = 2.0v; v i = v ih or v il; i o = 100 m a 1.8 2.0 1.8 high level output voltage ; all out p uts v cc = 2.7v; v i = v ih or v il; i o = 100 m a 2.5 2.7 2.5 v oh voltage all out uts v cc = 3.0v; v i = v ih or v il; i o = 100 m a 2.8 3.0 2.8 v v oh v cc = 4.5v; v i = v ih or v il; i o = 100 m a 4.3 4.5 4.3 v high level output voltage ; bus driver v cc = 3.0v; v i = v ih or v il; i o = 8ma 2.40 2.82 2.20 voltage; bus driver outputs v cc = 4.5v; v i = v ih or v il; i o = 16ma 3.60 4.20 3.50 v cc = 1.2v; v i = v ih or v il; i o = 100 m a 0 low l l t t v cc = 2.0v; v i = v ih or v il; i o = 100 m a 0 0.2 0.2 low level output voltage ; all out p uts v cc = 2.7v; v i = v ih or v il; i o = 100 m a 0 0.2 0.2 v ol voltage all out uts v cc = 3.0v; v i = v ih or v il; i o = 100 m a 0 0.2 0.2 v v ol v cc = 4.5v; v i = v ih or v il; i o = 100 m a 0 0.2 0.2 v low level output voltage ; bus driver v cc = 3.0v; v i = v ih or v il; i o = 8ma 0.20 0.40 0.50 voltage; bus driver outputs v cc = 4.5v; v i = v ih or v il; i o = 16ma 0.35 0.55 0.65 i i input leakage current v cc = 5.5v; v i = v cc or gnd 1.0 1.0 m a i oz 3-state output off-state current v cc = 5.5v; v i = v ih or v il; v o = v cc or gnd 5 10 m a i cc quiescent supply current; msi v cc = 5.5v; v i = v cc or gnd; i o = 0 20.0 160 m a d i cc additional quiescent supply current per input v cc = 2.7v to 3.6v; v i = v cc 0.6v 500 850 m a note: 1. all typical values are measured at t amb = 25 c.
philips semiconductors product specification 74lv373 octal d-type transparent latch (3-state) 1998 jun 10 6 ac characteristics gnd = 0v; t r = t f 2.5ns; c l = 50pf; r l = k condition limits symbol parameter waveform condition 40 to +85 c 40 to +125 c unit v cc (v) min typ 1 max min max 1.2 65 2.0 22 37 48 t phl/ t plh propagation delay d n to q n figure 1, 5 2.7 16 28 35 ns d n to q n 3.0 to 3.6 13 2 22 28 4.5 to 5.5 16 20 1.2 80 2.0 27 43 54 t phl/ t plh propagation delay le to q n figure 2, 5 2.7 20 26 33 ns le to q n 3.0 to 3.6 15 2 25 31 4.5 to 5.5 9.5 3 19 24 1.2 80 3 - state out p ut 2.0 27 46 58 t pzh/ t pzl 3-state out ut enable time oe tq figure 3 2.7 20 28 35 ns oe to q n 3.0 to 3.6 15 2 27 34 4.5 to 5.5 23 29 1.2 75 3 - state out p ut 2.0 27 46 58 t phz/ t plz 3-state out ut disable time oe tq figure 3 2.7 21 28 35 ns oe to q n 3.0 to 3.6 16 2 27 34 4.5 to 5.5 23 29 2.0 34 10 41 t w le pulse width high figure 2 2.7 25 8 30 ns 3.0 to 3.6 20 6 2 24 1.2 25 t setu p time d to le figure 4 2.0 17 9 20 ns t su set u p time d n to le fig u re 4 2.7 13 6 15 ns 3.0 to 3.6 10 5 2 12 1.2 15 t hold time d to le figure 4 2.0 5 5 5 ns t h hold time d n to le fig u re 4 2.7 5 3 5 ns 3.0 to 3.6 5 3 2 5 notes: 1. all typical values are measured at t amb = 25 c 2. typical values are measured at v cc = 3.3v 3. typical values are measured at v cc = 5.0v
philips semiconductors product specification 74lv373 octal d-type transparent latch (3-state) 1998 jun 10 7 ac waveforms v m = 1.5v at v cc 2.7v and 3.6v v m = 0.5v * v cc at v cc 2.7v and 4.5v v ol and v oh are the typical output voltage drop that occur with the output load. v x = v ol + 0.3v at v cc 2.7v and 3.6v v x = v ol + 0.1v cc at v cc < 2.7v and 4.5v v y = v oh 0.3v at v cc 2.7v and 3.6v v y = v oh 0.1v cc at v cc < 2.7v and 4.5v sv00662 v m d n input gnd v oh v ol v i q n output v m t plh t phl figure 1. data input (d n ) to output (q n ) propagation delays and the output transition times. sv00663 v m le input v ol gnd v oh v i q n output v m t plh t phl t w figure 2. latch enable input (le) pulse width, the latch enable input to output (q n ) propagation delays and the output transition times. sv00664 outputs disabled outputs enabled outputs enabled t phz t pzh t pzl t plz v x v y v m v m v m oe input v i v cc v ol v oh gnd gnd q n output low-to-off off-to-low q n output high-to-off off-to-high figure 3. 3-state enable and disable times. sv00665 v m d n input le input gnd gnd v i v i v m t su t su t h t h note: the shaded areas indicate when the input is permitted to change for predictable output performance. figure 4. data set-up and hold times for the d n input to the le input. test circuit switch position pulse generator r t v i d.u.t. v o c l r l = 1k v cc test circuit for outputs definitions v cc v i < 2.7v v cc test t plh/ t phl r t = termination resistance should be equal to z out of pulse generators. 2.7v 2.73.6v 4.5v v cc 50 pf sv00896 s 1 t plz/ t pzl t phz/ t pzh open 2 * v cc gnd r l = 1k open 2 * v cc gnd r l = load resistor c l = load capacitance includes jig and probe capacitiance. figure 5. load circuitry for switching times
philips semiconductors product specification 74lv373 octal d-type transparent latch (3-state) 1998 jun 10 8 dip20: plastic dual in-line package; 20 leads (300 mil) sot146-1
philips semiconductors product specification 74lv373 octal d-type transparent latch (3-state) 1998 jun 10 9 so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1
philips semiconductors product specification 74lv373 octal d-type transparent latch (3-state) 1998 jun 10 10 ssop20: plastic shrink small outline package; 20 leads; body width 5.3 mm sot339-1
philips semiconductors product specification 74lv373 octal d-type transparent latch (3-state) 1998 jun 10 11 tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1
philips semiconductors product specification 74lv373 octal d-type transparent latch (3-state) 1998 jun 10 12 philips semiconductors and philips electronics north america corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performanc e. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under a ny patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copy right, or mask work right infringement, unless otherwise specified. applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. life support applications philips semiconductors and philips electronics north america corporation products are not designed for use in life support appl iances, devices, or systems where malfunction of a philips semiconductors and philips electronics north america corporation product can reasonab ly be expected to result in a personal injury. philips semiconductors and philips electronics north america corporation customers using or sel ling philips semiconductors and philips electronics north america corporation products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors and philips electronics north america corporation for any damages resulting from such improper use or sale. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 definitions data sheet identification product status definition objective specification preliminary specification product specification formative or in design preproduction product full production this data sheet contains the design target or goal specifications for product development. specifications may change in any manner without notice. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. ? copyright philips electronics north america corporation 1998 all rights reserved. printed in u.s.a. print code date of release: 05-96 document order number: 9397-750-04447

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